1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to an automated method of varying stepper exposure dose across the surface of a wafer based upon across wafer variations in device characteristics, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11, such as doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped-polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
When the transistor 10 is operational, i.e., when it is turned xe2x80x9cONxe2x80x9d by applying an appropriate voltage to the gate electrode 14, a channel region 17, indicated by dashed lines, will be established in the substrate 1, between the source/drain regions 22. During operation, electrons will flow between the source/drain regions 22 in the channel region 17. The distance between the source/drain regions 22 is generally referred to as the xe2x80x9cchannel lengthxe2x80x9d of the transistor 10, and it approximately corresponds to the length 27 of the gate electrode 14. Channel length, at least in part, determines several performance characteristics of the transistor 10, such as drive current (Id), leakage currents, switching speed, etc.
As further background, as shown in FIGS. 2 and 3, a plurality of die 13 are fabricated above a surface 15 of a substrate or wafer 11. The die 13 are separated by scribe lines 21. Each of the die 13 contains many thousands of the transistors 10. As shown in FIG. 3, one or more illustrative test structures 23, such as a test transistor 29, are formed in the scribe lines 21 at various locations across the surface 15 of the wafer 11. For purposes of clarity, various process layers that are normally formed above the test structure 23, e.g., conductive lines and conductive contacts formed in layers of insulating material, have been omitted.
A plurality of such illustrative test transistors 29 are subjected to one or more electrical performance tests at various points during the process of forming a completed integrated circuit device on each die 13. For example, after an initial metal contact layer is formed, thereby allowing electrical coupling to the test transistor 29 by probing, the drive current of one or more of the test transistors 29 may be measured. The test transistors 29 are assumed to be representative of the transistors fabricated in the production die 13. Based upon such measurements, predictions may be made as to the performance characteristics of the completed integrated circuit devices formed on the die 13. For example, the measured drive current of one or more of the test transistors 29 may be used to predict the overall operating speed of completed integrated circuit devices.
Based upon the results of various electrical performance tests on the test structures 23 and/or completed integrated circuit devices, the wafer 11 may be considered to be comprised of multiple arbitrarily-defined regions, e.g., a center region 31, a middle region 33, and an edge region 35, in which integrated circuit devices formed therein share similar performance characteristics. The precise boundaries and shapes of these various regions are difficult to define. For example, the center region 31 may be defined by an outer radius 41 that is approximately one-third of a radius 43 of an active area 19. The middle region 33 may be defined by an outer radius 45 that is approximately two-thirds of the radius 43 of the active area 19 and an inner radius that corresponds to the outer radius 41 of the center region 31. The edge region 35 may be defined by the outer radius 43 and the inner radius 45. Although the depicted regions 31, 33 and 35 are depicted as having a generally circular or annular ring shape, in practice, they may be of any shape, e.g., oval, toroidal, etc., depending upon the results of the electrical testing.
Based upon experience, the electrical characteristics, e.g., drive current (Id), of the transistors 10 tend to vary across the surface 15 of the wafer 11. For example, the transistors 10 fabricated in the edge region 35 of the wafer 11 tend to have smaller drive currents (xe2x80x9cedge-coldxe2x80x9d) as compared to the transistors 10 fabricated in other regions of the wafer, e.g., the center region 31. Stated another way, the wafer 11 tends to exhibit certain across wafer performance characteristic xe2x80x9csignatures,xe2x80x9d like producing the transistors 10 with reduced drive currents in the edge region 35 of the wafer 11.
These across wafer performance variations may be a result of a variety of processing events. For example, such variations may be due to variations in manufactured gate lengths 27 across the surface of the wafer 11. Alternatively, these performance variations may be due to variations in the results of anneal processes performed on the transistors 10 fabricated in the edge region 35 of the wafer 11 as compared to, for example, the impact of such anneal processes on the transistors 10 fabricated in the center region 31. These variations may also be due to the inherent nature of fabricating the transistors 10 on the edge region 35 of the wafer 11, or they may be due to the particular processing tools used to fabricate the transistors 10 on the wafer 11.
Irrespective of the cause of such across wafer variations, such variations tend to be problematic in that the manufacturing operations are not as efficient as would otherwise be desired. For example, if it is desired to fabricate a certain number of high speed devices, additional wafers may have to be processed due to the fact that a certain number of devices manufactured in the center region 31 of the wafer 11 may have less than desirable performance characteristics, i.e., the operating speed of such transistors may be too slow. Thus, there is a need for an automated method and system of fabricating integrated circuit devices wherein variations in across wafer performance characteristics are reduced or eliminated.
The present invention is directed to solving, or at least reducing the effects of, some or all of the aforementioned problems.
The present invention is directed to a novel method of fabricating integrated circuit devices, and a system for accomplishing same. In one illustrative embodiment, the method comprises determining at least one electrical performance characteristic of a plurality of semiconductor devices formed above at least one semiconducting substrate, providing the determined electrical performance characteristics to a controller that determines, based upon the determined electrical characteristics, across-substrate variations in an exposure dose of a stepper exposure process to be performed on at least one subsequently processed substrate, and performing the stepper exposure process comprised of the across-substrate variations in exposure dose on the subsequently processed substrates. Through use of the present invention, the exposure dose may be varied on a flash-by-flash basis to compensate for deficiencies in device performance as reflected by the electrical tests.
In one embodiment, the system comprises a metrology tool for determining an electrical performance characteristic of a plurality of semiconductor devices formed above at least one substrate, a controller that determines, based upon the determined electrical performance characteristics, across-substrate variations in an exposure dose of a stepper exposure process to be performed on subsequently processed substrates, and a stepper tool that performs the stepper exposure process comprised of the across-substrate variations in exposure dose on the subsequently processed substrates.